The present invention relates to a multiplexer for connecting services on lower speed transmission lines such as circuit, frame relay, ATM (Asynchronous Transfer Mode) and so on, and ATM services on a higher speed transmission line.
Conventionally, a multiplexer for connecting services on lower speed transmission lines such as frame relay, ATM and so on, and ATM services on a higher speed transmission line is configured, for example, as illustrated in FIG. 11.
In FIG. 11, 2000 designates a higher speed line interface block which accommodates a higher speed transmission line for providing ATM services (hereinafter called the "higher speed ATM transmission line"); 1000 a lower speed ATM line interface block which accommodates a lower speed transmission line for providing ATM services (hereinafter called the "lower speed ATM transmission line"); 1100 a circuit emulation interface block which accommodates a lower speed transmission line for providing circuit services (hereinafter called the "circuit transmission line"); and 1200 a frame relay interface block which accommodates a lower speed transmission line for providing frame relay services such as HDLC (hereinafter called the "frame relay transmission line").
In the multiplexer as mentioned above, the lower speed ATM line interface block 1000, the circuit emulation interface block 1100 and the frame relay interface block 1200, which are associated with lower speed transmission lines, each terminate services provided by their respective transmission lines accommodated therein in a circuit termination block 1001 and a frame termination block 1002, generate ATM cells storing signals received by the terminated services in an AAL processing block 1003 and an ATM processing block 1004, and output the ATM cells to an internal transmission line 3000.
The higher speed ATM line interface block 2000, in turn, accepts ATM cells received from the lower speed transmission line 1000 at the ATM processing block 1004, multiplexes them at a physical layer processing block 1005, and transmits the multiplexed ATM cells onto the higher speed ATM transmission line.
On the other hand, signals received by the higher speed ATM line interface block 2000 from the higher speed ATM transmission line are separated in the physical layer processing block 1005 and outputted from the ATM processing block 1005 to the internal transmission line 3000 as ATM cells. These ATM cells are received respectively by the ATM processing blocks 1004 of the lower speed ATM line interface block 1000, the circuit emulation interface block 1100 and the frame relay interface block 1200, processed in the AAL processing block 1003, and thereafter converted into signals in formats in compliance with services on the lower speed transmission lines accommodated in the respective interfaces in the frame termination block 1002 and the circuit termination blocks 1001. The converted signals are transmitted onto the respective lower speed transmission lines.
Here, the AAL processing block 1003, which is a site for processing AAL layers, performs processing for adding AAL information to signals received by the circuit termination block 1001 and the frame termination block 1001 through services provided by lower speed transmission lines, processing for segmenting the signals with the information added thereto into pieces of 48-byte, which is the payload length of the ATM cell (segmentation), and so on, in order to provide services in accordance with services provided by corresponding lower speed transmission lines using payloads of ATM cells. In addition, the AAL processing block 1003 separates information of AAL included in received payloads of ATM cells, sends signals with the information of AAL excluded therefrom to the frame termination block 1002 and the circuit termination block 1001, and performs processing in accordance with the separated AAL information. The ATM processing block, in turn, is a site for performing ATM layers such as addition of an ATM header and so on.